In a general electronics circuitry, no matter whether it is realized through the use of discrete components and integrated circuits (IC) on a printed board assembly or as a tailored integrated circuit performing the entire desired function on a single integrated board assembly, there is, for instance, a need for filtering the DC supply from fluctuations, so called dI/dt noise. The noise in the integrated circuit chip is substantially generated as digital electronic functions are interconnected or decoupled. A reduction of the noises in the high frequency range is particularly important for high frequency circuits. An excessive generation of noise increases the requirements on the noise margin and other circuit parameters.
The closer the decoupling capacitators can be placed in relation to the noise source, i.e., for instance, the switching transistors, the more effective the decoupling will be, primarily due to a decreased inductance in series with the decoupling capacitance. On a board assembly, the decoupling capacitators must be placed closest to the noise generating IC-circuits, and a direct placing of decoupling capacitators on the integrated circuit chip is, of course, even better, since the decoupling is performed as close to the noise source as possible and powerful noise from RLC links through the bondings and the bonding wires will be suppressed and thus avoided. Due to the extremely low inductance in the power distribution lines on the chip itself, the decoupling capacitators on the chip also improve the frequency characteristics for the decoupling. It is, however, a problem that such an integrated capacitor normally requires a silicon surface, that can become relatively extensive to obtain a suitable capacitance value for the integrated capacitor.
U.S. Pat. No. 3,619,735 discloses a process and an integrated circuit, where a decoupling capacitator is provided underneath devices at the surface of an integrated circuit by creating a first epitaxial layer between a N.sup.+ substrate, which has a P.sup.+ zone diffused into it, and an epitaxial layer containing a N.sup.+ device, a P.sup.+ channel diffusion to the P.sup.+ zone formed in the substrate further serving as an attenuating resistor in combination with the coupling capacitance. The process does, however, require extra process steps in the manufacturing thereof.
Decoupling capacitators can also be created by distribution of capacitors in a carrier of the chip in an integrated circuit, which has been disclosed for example in EP-A2-0 262 493 and EP-A1-0 268 260, or in an LSI circuit, as in EP-A2-0 083 405. Thus, this means among other things that special steps must be performed in the manufacturing of the integrated circuit chip.
U.S. Pat. No. 4,937,640 to Shiba et al. discloses a capacitor formed on the semiconductor substrate and distributively connected between the power source wiring and the ground wirings. However, this solution may face yield problems due to the thin tantalium oxide layer on metal surfaces, particularly for larger areas as such layers often will show "pinholes", but also due to that such metal is relatively granulated and therefore rather uneven. Besides, there will be a need for special processing to achieve a reasonable value of capacitance in relation to area.
The method of designing application specific integrated circuits, so called AISC (Application Specific Integrated Circuit), consists in using predefined building blocks or standard cells from a library. The integration of decoupling capacitators in each such block or such cell constitutes the most effective decoupling method, since the noise is killed right at the source. Nor does the designer have to consider decoupling especially when cells or blocks from such a library are used.
The addition of such decoupling circuit elements does, however, consume the usually expensive silicon surface. If the decoupling capacitator is placed close to the noise source, the capacitor may be made smaller to a corresponding degree, since the decoupling will be more effective and smaller capacitors means less silicon surface.
The arrangement of the supply lines and earth connections is usually achieved by using metallization lines, which are broader than their corresponding signal lines. This is particularly true for high frequency IC-circuits. These supply lines are usually made at some metallization level during manufacturing, which layers are usually denoted with "m" plus a digit indicating the level, such as m2 (or m3 if available). Preferably, m2 or m3 is used to this end due to the higher conductivity of metallization layers higher up. The layer m1 and doped semiconductor layers are used for a local interconnection and for a definition of devices. The layers of these lower levels may be used in areas, which are completely covered by metallization in the m2 or m3 layers. Connections between the levels m1 and m2 and m2 and m3 respectively may then be achieved without using extra surface.
High quality capacitors having low values may be designed on one hand as a metal-metal capacitor, for instance, between m1 and m2, and on the other in a CMOS or a BiCMOS process making use of either a MOS structure (diffusion, polycrystalline silicon, m1 for connections) or as a reverse voltage pn junction (diffusion, m1 for connections).